Parallel streaming
Designed around multiple samples per clock cycle for applications that require higher FFT throughput.
FPGA signal-processing IP
Parallel SFF FFT IP
A configurable feed-forward FFT core under development for high-throughput FPGA applications, extending the published SFF architecture to parallel data paths.
Product development in progress
Architecture
FPGA-oriented streaming FFT
Feed-forward structure
Based on the SFF family of pipeline FFT architectures, with deterministic streaming data flow.
FPGA-aware mapping
Development targets efficient use of FPGA arithmetic and short-delay storage resources.
Configurable IP
The commercial implementation is being developed as a reusable, parameterized FPGA core.
Transform length
Configurable
Parallelism
P = 1, 2, 4, 8, …
Primary target
AMD / Xilinx FPGA
Interface
Streaming
Final supported configurations and implementation results will be published as development progresses.
Technical foundation
Peer-reviewed SFF architecture
C. Ingemarsson and O. Gustafsson, “SFF—The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture,” Journal of Signal Processing Systems, vol. 90, pp. 1583–1592, 2018.
The paper introduces the single-stream FPGA-optimized feedforward (SFF) FFT architecture and its FPGA-oriented use of short shift-register storage.
In preparation
A technical publication describing the parallel SFF extension is planned. A free preprint link will be added here when available.
Contact
Interested in the architecture or future evaluation access?
Technical and commercial enquiries are welcome while the IP core is in development.
carl@rejmyresp.comRejmyre SP AB · Sweden